The advent of multi-level metallization in ULSI circuits has placed stringent requirements on the planarity of the surface prior to metallization. Indeed, without some form of planarization between intervening layers of metallization, the topography of the lower layers is to some extent reflected in the topography of the insulating layer which forms the surface on which each additional level of metallization is formed. This is undesirable because it adds to the processing steps required, increases process complexity, and can lead to reduced device reliability.
There are two types of planarization which must be achieved; local and global. In local planarization, spaces between closely packed features are filled with an interlevel dielectric. Ideally, the dielectric provides void free filling and a locally planarized surface. In reality, however, the surface of the filled areas still reflect some of the underlying topography. When the wafer is covered by an interlevel dielectric layer whose exposed surface is flat, global planarization is achieved. Because the requirements of these two types of planarization are so different, separate processes are employed. Usually, local planarization is performed first followed by global planarization.
A number of local planarization processes are known and have proved successful. One such process involves atmospheric pressure chemical vapor deposition (APCVD) and sub-atmospheric chemical vapor deposition (SACVD) of TEOS and O.sub.3. These processes provide void-free filling of submicron spaces, with a relatively planar TEOS oxide film but global planarization cannot be achieved. The films provide good electrical characteristics in that the film has a high breakdown strength, is free of pin holes and has a low dielectric constant. This film becomes a part of the device structure.
Local planarization, though somewhat defective, can also be achieved with electron cyclotron resonance (ECR) deposited oxide films, however, the upper surface topology mirrors that of the underlying features. Other problems with this approach include safety concerns about high bias voltages that are used during deposition and unacceptable defect frequency. The films produced, however, have good electrical properties and become part of the device structure.
A third approach for local planarization involves low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD) TEOS oxide followed by deposition and reflow of boro phospho silicate glass (BPSG). This process is suitable for local planarization but it has not proved to be suitable for complete global planarization.
A fourth approach involves conventional sputter deposition of aluminum which produces planar films that form the interconnect. Step coverage of the film in contacts/vias, however, is poor thereby leading to incomplete filling. For this reason, CVD tungsten, which has good gap filling properties due to its highly conformal nature, is used to fill the contacts/vias, while aluminum is used to form the interconnect. However, this process sequence is complicated, and a single aluminum deposition to form the contact/via plugs and the interconnect is preferred. Recently, aluminum reflow that employs high temperature aluminum deposition to improve the step coverage has been demonstrated for void-free contact/via filling. However, this method is sensitive to the surface state of the wafer and does not reliably fill contacts/vias.
Local planarization is often followed by one of the global planarization techniques. One of the most common approaches involves coating the surface with a sacrificial dielectric followed by an etchback. This includes schemes such as SOG etchback and resist etchback, in which the wafer is coated with the dielectric. Because of the low surface tension of the dielectric during the coating process, the dielectric tends to flow into lower areas on the wafer which, on curing, forms a film that reduces the severity of the underlying topography. This reduced severity of topography is then transferred into the underlying dielectric (usually an oxide) via an etchback in which the sacrificial dielectric is removed. By repeating this cycle several times, a planarized surface is obtained. The biggest disadvantage of this process, however, is the multiple coating and etchback cycles required to obtain acceptable planarization. Often more than four cycles are required for adequate planarization.
To reduce the number of cycles required, blocking masks can be used, in which the sacrificial dielectric is coated and then patterned so that it fills up the dips in the topography. Another coat of the sacrificial dielectric is then applied to produce a planarized surface. This planar topography is transferred to the underlying interlevel dielectric via an etchback.
Another global planarizing approach that has gained some popularity is known as chemical mechanical polishing. In this technique, a polishing pad is used with a reactive slurry to polish the wafer surface until the surface is planarized. This technique, however, suffers from several limitations. The polishing rates are a function of many variables including feature size, aspect ratio, feature density and material type. Polishing rates also vary across the wafer and depend on the quality of the polishing pad. Post-process wafer clean-up is also an area of concern. When carefully applied, however, this technique has proved successful.
There are other approaches which are still in the experimental stage and involve new spin on or deposited dielectrics that provide good gap filling, electrical and thermal properties, and also provide global planarization. Examples of these materials include various types of fluorinated polymers, polyimides and siloxanes. All these approaches increase the planarization scale lengths appreciable (&gt;100 .mu.m), but still do not provide true global planarization.